Search - vhdl fir

[Mathimatics-Numerical algorithms] fir_rtl

Description: Simple fir digital filter
Platform: | Size: 1024 | Author: Digitalkurt | Hits:

[SCM] case4

Description: DA算法中的使用的查找表模块，本程序先设计查找表，然后设计4*4DA算法模块，之后进行位扩展和字扩展得到32阶滤波器程序.附带4各表，和FIR滤波器序数-DA algorithm used in the lookup table module, the design of the program first look-up table, and then design 4* 4DA algorithm module, after the word-bit expansion and extension of the procedure to be 32-order filter
Platform: | Size: 10240 | Author: 黄萌 | Hits:

[Special Effects] FIR

Description:
Platform: | Size: 5120 | Author: 司令 | Hits:

[Other] IIR

Description: 毕业设计：基于FPGA的IIR滤波器设计-The design for IIR digital filter based on FPGA
Platform: | Size: 472064 | Author: lzndcb | Hits:

[Software Engineering] filter_final

Description: compiled vhdl code for fir filter
Platform: | Size: 1210368 | Author: surya | Hits:

[Software Engineering] VHDL_FPGA_FILTER

Description: 用VHDL语言设计基于FPGA器件的高采样率FIR滤波器,基于VHDL与CPLD器件的FIR数字滤波器的设计-Design using VHDL language FPGA devices based on high sampling rate FIR filter, based on VHDL and CPLD devices, the design of FIR digital filter
Platform: | Size: 913408 | Author: 玉玲 | Hits:

[VHDL-FPGA-Verilog] beta

Description: Fir verilog code implemented to find out the output of fir filter
Platform: | Size: 1024 | Author: dheeru | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[VHDL-FPGA-Verilog] FirFilter

Description: 对称型线性相位FIR滤波器的VHDL源程序，比直接型FIR滤波器速度快一半-VHDLSourceProgramofFirFilter
Platform: | Size: 1024 | Author: 杨波 | Hits:

[DSP program] fir8

Description: 用verilog编写的8阶串行fir滤波器-verilog vhdl fir
Platform: | Size: 1024 | Author: 2000flash | Hits:

[VHDL-FPGA-Verilog] 3

Description: 基于FPGA的高速高阶FIR滤波器设计基于FPGA的高速高阶FIR滤波器设计-High-speed FPGA-based FIR filter design for high-end high-end high-speed FPGA-based FIR filter design
Platform: | Size: 5903360 | Author: 南才北往 | Hits:

[VHDL-FPGA-Verilog] 4

Description: 基于FPGA的FIR数字滤波器的设计与实现,基于FPGA的FIR数字滤波器的设计与实现-FPGA-based FIR digital filter design and implementation of FPGA-Based FIR Digital Filter Design and Implementation
Platform: | Size: 2337792 | Author: 南才北往 | Hits:

[VHDL-FPGA-Verilog] 3

Description: FIR数字滤波器的优化与验证 -FIR digital filter optimization and verification FIR digital filter optimization and verification
Platform: | Size: 336896 | Author: 南才北往 | Hits:

[DSP program] fri

Description: 滤波器的设计的，用于FIR滤波器的设计和应用-The design of filters for the FIR filter design and application
Platform: | Size: 650240 | Author: qian | Hits:

[DSP program] FIR

Description: 详细的介绍的通过DSP编写滤波器的过程，图形并茂，非常好的资料，希望与大家共享，共同进步,超棒的资料-Detail the preparation of the filter through the process of DSP, graphics and Mao, very good information, I hope to share with you and common progress, great information
Platform: | Size: 247808 | Author: 爷们 | Hits:

[VHDL-FPGA-Verilog] filter_vhdl

Description: vhdl语言编写的fir和iir滤波器程序。在quartus上仿真通过。-vhdl language program fir and iir filters. Quartus adopted in the simulation.
Platform: | Size: 37888 | Author: lmy | Hits:

[VHDL-FPGA-Verilog] fir_lms

Description: 一个不错的关于lms算法的verilog代码，算然只有两级，但是对了解lms用HDL描述有很好的理解作用。希望对大家有用~-A good lms algorithm on the verilog code, development environment, I can not find, even if the vhdl it! We hope to be useful
Platform: | Size: 1024 | Author: onion | Hits:

[ARM-PowerPC-ColdFire-MIPS] VHDL_100_1

Description: 第43例四位移位寄存器第44例寄存／计数器第45例顺序过程调用第46例 VHDL中generic缺省值的使用第47例无输入元件的模拟第48例测试激励向量的编写第49例 delta延迟例释第50例惯性延迟分析第51例传输延迟驱动优先第52例多倍（次）分频器第53例三位计数器与测试平台第54例分秒计数显示器的行为描述6 第55例地址计数器第56例指令预读计数器第57例加.c减.c乘指令的译码和操作第58例 2－4译码器结构描述第59例 2－4译码器行为描述第60例转换函数在元件例示中的应用第61例基于同一基类型的两分辨类型的赋值相容问题第62例最大公约数的计算第63例最大公约数七段显示器编码第64例交通灯控制器第65例空调系统有限状态自动机第66例 FIR滤波器第67例五阶椭圆滤波器第68例闹钟系统的控制第69例闹钟系统的译码第70例闹钟系统的移位寄存器第71例闹钟系统的闹钟寄存器和时间计数器第72例闹钟系统的显示驱动器
Platform: | Size: 340992 | Author: zyw | Hits:

[VHDL-FPGA-Verilog] fir_liujiao

Description: 利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter
Platform: | Size: 96256 | Author: juan | Hits:

[Mathimatics-Numerical algorithms] Adaptive_FIR_Equalizer_With_Continuous-Time_Wide-

Description: Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line
Platform: | Size: 2061312 | Author: asia | Hits:

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[Mathimatics-Numerical algorithms] fir_rtl

[SCM] case4

[Special Effects] FIR

[Other] IIR

[Software Engineering] filter_final

[Software Engineering] VHDL_FPGA_FILTER

[VHDL-FPGA-Verilog] beta

[Linux-Unix] Linux_bc

[VHDL-FPGA-Verilog] FirFilter

[DSP program] fir8

[VHDL-FPGA-Verilog] 3

[VHDL-FPGA-Verilog] 4

[VHDL-FPGA-Verilog] 3

[DSP program] fri

[DSP program] FIR

[VHDL-FPGA-Verilog] filter_vhdl

[VHDL-FPGA-Verilog] fir_lms

[ARM-PowerPC-ColdFire-MIPS] VHDL_100_1

[VHDL-FPGA-Verilog] fir_liujiao

[Mathimatics-Numerical algorithms] Adaptive_FIR_Equalizer_With_Continuous-Time_Wide-

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